Zilog Z80180 Manuel d'utilisateur télécharger pdf (Page 32)

100

101

Z8018x

Family MPU User Manual

UM005003-0703

Figure 7. I/O Read and Write Cycles with IOC = 1 Timing Diagram

When IOC is 0, the timing of the IORQ and RD signals match the timing

required by the Z80 family of peripherals. The IORQ

and RD signals go

active as a result of the rising edge of T2. This timing allows the Z8X180

to satisfy the setup times required by the Z80 peripherals on those two

signals (Figure ).

Figure 8. I/O Read and Write cycles with IOC = 0 Timing Diagram

For the remainder of this document, assume that M1E is 0 and IOC is 0.

Phi

IORQ

Phi

IORQ

1 2 ... 27 28 29 30 31 32 33 34 35 36 37 ... 325 326

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Zilog Z80180 Manuel d'utilisateur Page 32

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