Zilog Z16F2810 Manuel d'utilisateur

Copyright ©2011 Zilog®, Inc. All rights reserved.www.zilog.comUser ManualZNEO® CPU CoreHigh-Performance 16-Bit MicrocontrollersUM018809-0611

List of Figures UM018809-0611xZNEO® CPU CoreUser Manual

COM Instruction UM018809-061184ZNEO® CPU CoreUser ManualCOMDefinitionComplement SyntaxCOM dstOperationdst  ~dstDescriptionThe contents of the dest

UM018809-0611 COM InstructionZNEO® CPU CoreUser Manual85ExampleBefore: R7=7F37_B2D3H (0111_1111_0011_0111_1011_0010_1101_0011B)COM R7 ;Object code:

CP Instruction UM018809-061186ZNEO® CPU CoreUser ManualCPDefinitionCompareSyntaxCP dst, srcOperationdst – srcDescriptionThe source operand is compa

UM018809-0611 CP InstructionZNEO® CPU CoreUser Manual87Syntax and OpcodesInstruction, Operands Word 0 Word 1 Word 2CP Rd, #imm32 {AADH, Rd} imm[31:1

CP Instruction UM018809-061188ZNEO® CPU CoreUser ManualExamplesBefore: R3=16H, R11=20HCP R3, R11 ;Object code: A5B3After: Flags C, S=1; Z, V, B=0Be

UM018809-0611 CPC InstructionZNEO® CPU CoreUser Manual89CPCDefinitionCompare with CarrySyntaxCPC dst, srcOperationdst – src – C DescriptionThe sourc

CPC Instruction UM018809-061190ZNEO® CPU CoreUser ManualSyntax and OpcodesInstruction, OperandsExtendPrefix Word 0 Word 1 Word 2CPC Rd, #imm32 000

UM018809-0611 CPC InstructionZNEO® CPU CoreUser Manual91ExamplesBefore: R3=16H, R11=16H, Z=1, C=0CPC R3, R11 ;Object code: 0007 A5B3After: Flags Z=1

CPCZ Instruction UM018809-061192ZNEO® CPU CoreUser ManualCPCZDefinitionCompare with Carry to ZeroSyntaxCPCZ dstOperationdst – 0 – CDescriptionThe v

UM018809-0611 CPCZ InstructionZNEO® CPU CoreUser Manual93Syntax and OpcodesExamplesBefore: R3=FFFF_B0D4H, FFFF_B0D4H=0000H, Z=1, C=0CPCZ.W (R3) ;Obj

UM018809-0611 List of TablesZNEO® CPU CoreUser ManualxiList of TablesTable 1. Instruction Execution Cycles . . . . . . . . . . . . . . . . . . . .

CPZ Instruction UM018809-061194ZNEO® CPU CoreUser ManualCPZDefinitionCompare to ZeroSyntaxCPZ dstOperationdst – 0DescriptionThe value zero is compa

UM018809-0611 CPZ InstructionZNEO® CPU CoreUser Manual95Syntax and OpcodesExamplesBefore: R3=FFFF_B0D4H, FFFF_B0D4H=0000HCPZ.W (R3) ;Object Code: AC

DEC Instruction UM018809-061196ZNEO® CPU CoreUser ManualDECDefinitionDecrement SyntaxDEC dstOperationdst  dst – 1DescriptionThe contents of the de

UM018809-0611 DEC InstructionZNEO® CPU CoreUser Manual97ExamplesBefore: R3=FFFF_B024H, FFFF_B02CH=702EHDEC.W 8(R3) ;Object Code: ADF3 4008After: FFF

DI Instruction UM018809-061198ZNEO® CPU CoreUser ManualDIDefinitionDisable InterruptsSyntaxDIOperationFLAGS[0]  0DescriptionThe Master Interrupt E

UM018809-0611 DI InstructionZNEO® CPU CoreUser Manual99After: IRQE=0 (Vectored interrupt requests are globally disabled.)

DJNZ Instruction UM018809-0611100ZNEO® CPU CoreUser ManualDJNZDefinitionDecrement and Jump if Non-ZeroSyntaxDJNZ dst, urel4Operationdst  dst – 1i

UM018809-0611 DJNZ InstructionZNEO® CPU CoreUser Manual101Flags are set based on the 32-bit decrement register value.Syntax and OpcodesExampleDJNZ c

EI Instruction UM018809-0611102ZNEO® CPU CoreUser ManualEIDefinitionEnable InterruptsSyntaxEIOperationFLAGS[0]  1DescriptionThe Master Interrupt E

UM018809-0611 EXT InstructionZNEO® CPU CoreUser Manual103EXTDefinitionExtendSyntaxEXT dst, srcOperationdst  srcDescriptionThis instruction loads an

List of Tables UM018809-0611xiiZNEO® CPU CoreUser Manual

EXT Instruction UM018809-0611104ZNEO® CPU CoreUser ManualExamplesBefore: R11=xxxx_xx86HEXT.SB R3, R11 ;Object code: 42B3After: R3=FFFF_FF86H, Flags

UM018809-0611 HALT InstructionZNEO® CPU CoreUser Manual105HALTDefinitionHalt ModeSyntaxHALTOperationEnter Halt mode.DescriptionThe HALT instruction

ILL Instruction UM018809-0611106ZNEO® CPU CoreUser ManualILLDefinitionIllegal InstructionOperationSP  SP – 2(SP)  {00H, FLAGS[7:0]}SP  SP – 4

UM018809-0611 ILL InstructionZNEO® CPU CoreUser Manual107An IRET instruction must not be used to end an Illegal Instruction exception service rou-ti

INC Instruction UM018809-0611108ZNEO® CPU CoreUser ManualINCDefinitionIncrementSyntaxINC dstOperationdst  dst + 1DescriptionThe contents of the de

UM018809-0611 INC InstructionZNEO® CPU CoreUser Manual109ExamplesBefore: R3=FFFF_B024H, FFFF_B02CH=702EHINC.W 8(R3) ;Object Code: ADE3 4008After: FF

IRET Instruction UM018809-0611110ZNEO® CPU CoreUser ManualIRETDefinitionInterrupt ReturnSyntaxIRETOperationNormal IRET Chained IRETPC  (SP) PC 

UM018809-0611 IRET InstructionZNEO® CPU CoreUser Manual111If IRET chains to another interrupt service routine, it clears the IRQE flag and leaves al

JP Instruction UM018809-0611112ZNEO® CPU CoreUser ManualJPDefinitionJumpSyntaxJP dstOperationPC  destination addressDescriptionThe unconditional j

UM018809-0611 JPA InstructionZNEO® CPU CoreUser Manual113JPADefinitionJump AbsoluteSyntaxJP dstOperationPC  dstDescriptionJPA replaces the contents

UM018809-0611 Manual ObjectivesZNEO® CPU CoreUser ManualxiiiManual ObjectivesThis user manual describes the CPU architecture and instruction set com

JP cc Instruction UM018809-0611114ZNEO® CPU CoreUser ManualJP CCDefinitionJump ConditionallySyntaxJP cc, dstOperationif cc (condition code) is true

UM018809-0611 LD InstructionZNEO® CPU CoreUser Manual115LDDefinitionLoadSyntaxLD dst, srcOperationdst  srcDescriptionThe contents of the source ope

LD Instruction UM018809-0611116ZNEO® CPU CoreUser ManualFlagsSyntax and Opcodes76543210C Z S V B CIRQE IRQE––––*–––LegendC = No change.Z = No chang

UM018809-0611 LD InstructionZNEO® CPU CoreUser Manual117LD (––Rd), Rs {10H, Rs, Rd}LD (Rd++), #imm32 {09FH, Rd} imm[31:16] imm[15:0]LD (Rd++), #simm

LD Instruction UM018809-0611118ZNEO® CPU CoreUser ManualExamplesBefore: R13=xxxx_xxxxHLD R13, #34H ;Object Code: 3D34After: R13=0000_0034HBefore: R

UM018809-0611 LD InstructionZNEO® CPU CoreUser Manual119Before: R12=FFFF_B034H, FFFF_B034H=FFHLD.SB R13, (R12) ;Object Code: 1CCDAfter: R13=FFFF_FFF

LD cc Instruction UM018809-0611120ZNEO® CPU CoreUser ManualLD CCDefinitionLoad Condition CodeSyntaxLD cc, dstOperationdst  ccDescriptionThis instr

UM018809-0611 LDES InstructionZNEO® CPU CoreUser Manual121LDESDefinitionLoad and Extend SignSyntaxLDES dstOperationdst[31:0]  SDescriptionThis inst

LEA Instruction UM018809-0611122ZNEO® CPU CoreUser ManualLEADefinitionLoad Effective addressSyntaxLEA dst, srcOperationdst  effective addressDescr

UM018809-0611 LEA InstructionZNEO® CPU CoreUser Manual123ExampleBefore: FP=FFFF_B016HLEA R11, 15H(FP) ;Object code: 4D5BAfter: R11=FFFF_B02BH

Manual Objectives UM018809-0611xivZNEO® CPU CoreUser ManualInterruptsIntroduces the use of vectored and polled interrupts to service interrupt requ

LINK Instruction UM018809-0611124ZNEO® CPU CoreUser ManualLINKDefinitionLink Frame PointerSyntaxLINK #uimm8OperationSP  SP – 4 (SP)  R14R14 

UM018809-0611 MUL InstructionZNEO® CPU CoreUser Manual125MULDefinitionMultiplySyntaxMUL dst, srcOperationdst  dst  srcDescriptionThis instruction

MUL Instruction UM018809-0611126ZNEO® CPU CoreUser ManualExampleBefore: R4=0000_0086H, R5=8000_0053HMUL R4, R5 ;Object Code: B254After: R4=0000_2B7

UM018809-0611 NEG InstructionZNEO® CPU CoreUser Manual127NEGDefinitionNegateSyntax NEG dstOperationdst  0 – dstDescriptionThe contents of the desti

NEG Instruction UM018809-0611128ZNEO® CPU CoreUser ManualExampleBefore: R7=7F37_B2D3H (0111_1111_0011_0111_1011_0010_1101_0011B)NEG R7 ;Object code

UM018809-0611 NOFLAGS InstructionZNEO® CPU CoreUser Manual129NOFLAGSDefinitionNo Flags ModifierSyntaxNFLAGSOperationModify the next instruction to s

NOP Instruction UM018809-0611130ZNEO® CPU CoreUser ManualNOPDefinitionNo OperationSyntaxNOPOperationNoneDescriptionNo action is performed by this i

UM018809-0611 OR InstructionZNEO® CPU CoreUser Manual131ORDefinitionLogical ORSyntaxOR dst, srcOperationdst  dst OR src DescriptionThe source opera

OR Instruction UM018809-0611132ZNEO® CPU CoreUser ManualFlags are set based on the memory destination size, or 32 bits for register destinations.Sy

UM018809-0611 OR InstructionZNEO® CPU CoreUser Manual133ExamplesBefore: R1[7:0]=38H (0011_1000B), R14[7:0]=8DH (1000_1101B)OR R1, R14 ;Object Code:

UM018809-0611 Manual ObjectivesZNEO® CPU CoreUser ManualxvExample 1: R1 is set to F8H.Example 2: 32-bit hexadecimal value 1234_5678HBit NumberingBi

POP Instruction UM018809-0611134ZNEO® CPU CoreUser ManualPOPDefinitionPOP ValueSyntaxPOP dstOperationDescriptionThe POP instruction loads the desti

UM018809-0611 POP InstructionZNEO® CPU CoreUser Manual135Syntax and OpcodesExampleBefore: SP=FFFF_DB22H, FFFF_DB22H=8642POP.SW R6 ;Object Code: 1FF6

POPF Instruction UM018809-0611136ZNEO® CPU CoreUser ManualPOPFDefinitionPOP FlagsSyntaxPOPFOperationFLAGS[7:0]  + 1(SP)SP  SP + 2DescriptionThe

UM018809-0611 POPMLO InstructionZNEO® CPU CoreUser Manual137POPMLODefinitionSyntaxOperationDescriptionFlagsSyntax and OpcodesExample

POPMHI Instruction UM018809-0611138ZNEO® CPU CoreUser ManualPOPMHIDefinitionPOP MultipleSyntaxPOPMLO maskPOPMHI maskOperationDescriptionExecution

UM018809-0611 POPMHI InstructionZNEO® CPU CoreUser Manual139The assembler also accepts statements using the combined POPM mnemonic with an immediate

PUSH Instruction UM018809-0611140ZNEO® CPU CoreUser ManualPUSHDefinitionPUSH ValueSyntaxPUSH srcOperationDescriptionThe PUSH instruction decrements

UM018809-0611 PUSH InstructionZNEO® CPU CoreUser Manual141Syntax and OpcodesExamplesBefore: SP=FFFF_DB24H, R6=FFFF_8642PUSH.W R6 ;Object Code: 166FA

PUSHF Instruction UM018809-0611142ZNEO® CPU CoreUser ManualPUSHFDefinitionPUSH FlagsSyntaxPUSHFOperationSP  SP – 2(SP)  {00H, FLAGS[7:0]}Descript

UM018809-0611 PUSHMHI InstructionZNEO® CPU CoreUser Manual143PUSHMHIDefinitionSyntaxOperationDescriptionFlagsSyntax and OpcodesExample

Manual Objectives UM018809-0611xviZNEO® CPU CoreUser ManualUse of Initial Uppercase LettersInitial uppercase letters designate settings, modes, and

PUSHMLO Instruction UM018809-0611144ZNEO® CPU CoreUser ManualPUSHMLODefinitionPUSH MultipleSyntaxPUSHMHI maskPUSHMLO maskOperation (Assembly Langu

UM018809-0611 PUSHMLO InstructionZNEO® CPU CoreUser Manual145For example, the following statement produces the same object code as the previous two-

RET Instruction UM018809-0611146ZNEO® CPU CoreUser ManualRETDefinitionReturnSyntaxRETOperationPC  (SP)SP  SP + 4DescriptionThis instruction retu

UM018809-0611 RL InstructionZNEO® CPU CoreUser Manual147RLDefinitionRotate LeftSyntaxRL dst, srcOperationDescriptionThe destination operand contents

RL Instruction UM018809-0611148ZNEO® CPU CoreUser ManualSyntax and OpcodesExampleBefore: R7=7F37_B2D3H (0111_1111_0011_0111_1011_0010_1101_0011B)RL

UM018809-0611 SBC InstructionZNEO® CPU CoreUser Manual149SBCDefinitionSubtract with CarrySyntaxSBC dst, srcOperationdst  dst – src – C DescriptionT

SBC Instruction UM018809-0611150ZNEO® CPU CoreUser ManualFlags are set based on the memory destination size, or 32 bits for register destinations.S

UM018809-0611 SBC InstructionZNEO® CPU CoreUser Manual151ExamplesBefore: R3=16H, R11=20H, C=0SBC R3, R11 ;Object code: 0007 A1B3After: R3=FFFF_FFF6H

SDIV Instruction UM018809-0611152ZNEO® CPU CoreUser ManualSDIVDefinitionSigned DivideSyntaxSDIV dst, srcOperationsrc  Remainder (dst/src)dst  In

UM018809-0611 SDIV InstructionZNEO® CPU CoreUser Manual153FlagsSyntax and OpcodesExampleBefore: R4=FFFF_FFE5H (–27), R5=0000_0005HSDIV R4, R5 ;Objec

UM018809-0611 Architectural OverviewZNEO® CPU CoreUser Manual1Architectural OverviewZilog’s ZNEO CPU meets the continuing demand for faster and more

SLL Instruction UM018809-0611154ZNEO® CPU CoreUser ManualSLLDefinitionShift Left LogicalSyntaxSLL dst, srcOperationDescriptionThe destination opera

UM018809-0611 SLL InstructionZNEO® CPU CoreUser Manual155Syntax and OpcodesExampleBefore: R7=7F37_B2D3H (0111_1111_0011_0111_1011_0010_1101_0011B)SL

SLLX Instruction UM018809-0611156ZNEO® CPU CoreUser ManualSLLXDefinitionShift Left Logical, ExtendedSyntaxSLLX dst, srcOperationDescriptionThe dest

UM018809-0611 SLLX InstructionZNEO® CPU CoreUser Manual157Flags are set based on the 32-bit destination register value.Syntax and OpcodesExampleBefo

SMUL Instruction UM018809-0611158ZNEO® CPU CoreUser ManualSMULDefinitionSigned MultiplySyntaxSMUL dst, srcOperationdst  (dst  src)[31:0]src  (ds

UM018809-0611 SMUL InstructionZNEO® CPU CoreUser Manual159ExampleBefore: R4=FFFF_FFE5H (–27), R5=0000_0005HSMUL R4, R5 ;Object code B154After: R4=FF

SRA Instruction UM018809-0611160ZNEO® CPU CoreUser ManualSRADefinitionShift Right ArithmeticSyntaxSRA dst, srcOperationDescriptionThis instruction

UM018809-0611 SRA InstructionZNEO® CPU CoreUser Manual161Syntax and OpcodesExamplesBefore: R7=7F37_B2D3H (0111_1111_0011_0111_1011_0010_1101_0011B)S

SRAX Instruction UM018809-0611162ZNEO® CPU CoreUser ManualSRAXDefinitionShift Right Arithmetic, ExtendedSyntaxSRAX dst, srcOperationDescriptionThis

UM018809-0611 SRAX InstructionZNEO® CPU CoreUser Manual163FlagsFlags are set based on the 32-bit destination register value.Syntax and OpcodesExampl

Architectural Overview UM018809-06112ZNEO® CPU CoreUser ManualProgram ControlZNEO CPU is controlled by a program stored in memory as object code. A

SRL Instruction UM018809-0611164ZNEO® CPU CoreUser ManualSRLDefinitionShift Right LogicalSyntaxSRL dst, srcOperationDescriptionThe destination oper

UM018809-0611 SRL InstructionZNEO® CPU CoreUser Manual165Syntax and OpcodesExampleBefore: R7=8F37_B2D3H (1000_1111_0011_0111_1011_0010_1101_0011B)SR

SRLX Instruction UM018809-0611166ZNEO® CPU CoreUser ManualSRLXDefinitionShift Right Logical, ExtendedSyntaxSRLX dst, srcOperationDescriptionThe des

UM018809-0611 SRLX InstructionZNEO® CPU CoreUser Manual167Flags are set based on the 32-bit destination register value.Syntax and OpcodesExampleBefo

STOP Instruction UM018809-0611168ZNEO® CPU CoreUser ManualSTOPDefinitionSTOP ModeSyntaxSTOPOperationStop ModeDescriptionThis instruction puts the Z

UM018809-0611 SUB InstructionZNEO® CPU CoreUser Manual169SUBDefinitionSubtractSyntaxSUB dst, srcOperationdst  dst – src DescriptionThis instruction

SUB Instruction UM018809-0611170ZNEO® CPU CoreUser ManualSyntax and OpcodesInstruction, Operands Word 0 Word 1 Word 2SUB Rd, #imm32 {AA9H, Rd} imm[

UM018809-0611 SUB InstructionZNEO® CPU CoreUser Manual171ExamplesBefore: R3=16H, R11=20HSUB R3, R11 ;Object code: A1B3After: R3=FFFF_FFF6H, Flags C,

TCM Instruction UM018809-0611172ZNEO® CPU CoreUser ManualTCMDefinitionTest Complement Under MaskSyntaxTCM dst, srcOperation~dst AND srcDescriptionT

UM018809-0611 TCM InstructionZNEO® CPU CoreUser Manual173Syntax and OpcodesInstruction, Operands Word 0 Word 1 Word 2TCM Rd, #imm32 {AAFH, Rd} imm[3

UM018809-0611 Architectural OverviewZNEO® CPU CoreUser Manual3Fetch UnitThe Fetch Unit’s primary function is to fetch opcodes and operand words (inc

TCM Instruction UM018809-0611174ZNEO® CPU CoreUser ManualExamplesBefore: R1[7:0]=38H (0011_1000B), R14[31:8]=0000_00H, R14[7:0]=08H (0000_1000B)TCM

UM018809-0611 TM InstructionZNEO® CPU CoreUser Manual175TMDefinitionTest Under MaskSyntaxTM dst, srcOperationdst AND srcDescriptionThis instruction

TM Instruction UM018809-0611176ZNEO® CPU CoreUser ManualSyntax and OpcodesInstruction, Operands Word 0 Word 1 Word 2TM Rd, #imm32 {AAEH, Rd} imm[31

UM018809-0611 TM InstructionZNEO® CPU CoreUser Manual177ExamplesBefore: R1[7:0]=38H (0011_1000B), R14[31:8]=0000_00H, R14[7:0]=08H (0000_1000B)TM R1

TRAP Instruction UM018809-0611178ZNEO® CPU CoreUser ManualTRAPDefinitionSoftware TrapSyntaxTRAP VectorOperationSP  SP – 2(SP)  {00H, FLAGS[7:0]}

UM018809-0611 TRAP InstructionZNEO® CPU CoreUser Manual179ExampleBefore: PC=0000_044EH, SP=FFFF_DB22H, 0000_03FCH=0000_EE00HTRAP #FFH ;Object Code:

UDIV Instruction UM018809-0611180ZNEO® CPU CoreUser ManualUDIVDefinitionUnsigned DivideSyntaxUDIV dst, srcOperationsrc  Remainder (dst/src)dst 

UM018809-0611 UDIV InstructionZNEO® CPU CoreUser Manual181Syntax and OpcodesExampleBefore: R4=FFFF_FFE5H, R5=0000_0005HUDIV R4, R5 ;Object code AE54

UDIV64 Instruction UM018809-0611182ZNEO® CPU CoreUser ManualUDIV64DefinitionUnsigned 64-bit DivideSyntaxUDIV dst, srcOperationdst[63;32]  Integer

UM018809-0611 UDIV64 InstructionZNEO® CPU CoreUser Manual183Case 2: If the divisor is zero, the destination, source, and flags registers are unchang

UM018809-0611iiZNEO® CPU CoreUser ManualThis publication is subject to replacement by a later edition. To determine whether a later edition exists,

Architectural Overview UM018809-06114ZNEO® CPU CoreUser ManualExecution UnitThe Execution Unit performs the processing functions required by the in

UMUL Instruction UM018809-0611184ZNEO® CPU CoreUser ManualUMULDefinitionUnsigned MultiplySyntaxUMUL dst, srcOperationdst (dst  src)[31:0]src

UM018809-0611 UMUL InstructionZNEO® CPU CoreUser Manual185ExampleBefore: R4=FFFF_FFE5H, R5=0000_0005HUMUL R4, R5 ;Object code B054After: R4=FFFF_FF7

UNLINK Instruction UM018809-0611186ZNEO® CPU CoreUser ManualUNLINKDefinitionUnlink Frame PointerSyntaxUNLINKOperationSP  R14R14  (SP)SP  SP +

UM018809-0611 WDT InstructionZNEO® CPU CoreUser Manual187WDTDefinitionWatchdog Timer RefreshSyntaxWDTOperationNoneDescriptionEnable the Watchdog Tim

XOR Instruction UM018809-0611188ZNEO® CPU CoreUser ManualXORDefinitionLogical Exclusive ORSyntaxXOR dst, srcOperationdst dst XOR srcDescriptionTh

UM018809-0611 XOR InstructionZNEO® CPU CoreUser Manual189Flags are set based on the memory destination size, or 32 bits for register destinations.Sy

XOR Instruction UM018809-0611190ZNEO® CPU CoreUser ManualExamplesBefore: R1[7:0]=38H (0011_1000B), R14[7:0]=8DH (1000_1101B)XOR R1, R14 ;Object Cod

ZNEO® CPU CoreUser Manual19UM018809-0611 IndexIndexNumerics16-bit addressing 16, 2932-bit addressing 29Aabbreviationsmiscellaneous 66opcode 55symbolic

19ZNEO® CPU CoreUser ManualIndex UM018809-0611instruction 79CALLA instruction 81carry flag 10caution, meaning of xviceiling function 7clear register i

ZNEO® CPU CoreUser Manual19UM018809-0611 IndexEeffective address16-bit 29loading 33register indirect 32EI instruction 41, 102enable interrupt 41, 102e

UM018809-0611 Architectural OverviewZNEO® CPU CoreUser Manual5•All 32 bits of a source or destination ALU Register are used for arithmetic and logic

19ZNEO® CPU CoreUser ManualIndex UM018809-0611enable 41nesting 45polled 46priority 45processing 42return 44, 110software 46stack behavior 43vectored 4

ZNEO® CPU CoreUser Manual19UM018809-0611 Indexassembly language 21meaning of 2MSB, meaning xvmsb, meaning xvMUL instruction 125multiple pop instructio

19ZNEO® CPU CoreUser ManualIndex UM018809-0611program counteras base address 34description 4loading 34overflow 50program, processor 2pseudo-op 21PUSH

ZNEO® CPU CoreUser Manual19UM018809-0611 IndexSP register 36space, address 15SPOV register 9, 50SRA instruction 160SRAX instruction 162SRL instruction

19ZNEO® CPU CoreUser ManualIndex UM018809-0611WDT instruction 187width, bus 19word data size 32XXOR instruction 188ZZ condition code 12zero extension

UM018809-0611 Customer SupportZNEO® CPU CoreUser Manual199Customer SupportTo share comments, get your technical questions answered, or report issues

Customer Support UM018809-0611200ZNEO® CPU CoreUser Manual

Architectural Overview UM018809-06116ZNEO® CPU CoreUser ManualInstructions always begin at an even address; therefore, instruction fetches are not

UM018809-0611 Architectural OverviewZNEO® CPU CoreUser Manual7Execution cycles can be affected by the following factors:•The symbol bus_time stands

Architectural Overview UM018809-06118ZNEO® CPU CoreUser Manual•For LD and LEA instructions, a delay cycle is inserted if a register is loaded immed

UM018809-0611 Architectural OverviewZNEO® CPU CoreUser Manual9Program Counter Overflow RegisterThe Program Counter Overflow Register (PCOV) implemen

Architectural Overview UM018809-061110ZNEO® CPU CoreUser ManualFlag settings depend on the data size of the result, which can be 8 bits (Byte), 16

UM018809-0611 Architectural OverviewZNEO® CPU CoreUser Manual11Blank FlagFor some arithmetic, logical, and load operations, the Blank (B) flag is se

Architectural Overview UM018809-061112ZNEO® CPU CoreUser Manualcalled the condition code (cc), which are assembled into each conditional jump opcod

UM018809-0611 Architectural OverviewZNEO® CPU CoreUser Manual13CPU Control Register (CPUCTL)Bits [1:0] of the CPU Control Register (see Table 4 on p

UM018809-0611 Revision HistoryZNEO® CPU CoreUser ManualiiiRevision HistoryEach instance in the Revision History table below reflects a change to th

Architectural Overview UM018809-061114ZNEO® CPU CoreUser Manual

UM018809-0611 Address SpaceZNEO® CPU CoreUser Manual15Address SpaceThe ZNEO CPU has a unique memory architecture with a unified address space. It su

Address Space UM018809-061116ZNEO® CPU CoreUser ManualMemory MapFigure 3 displays a memory map of the ZNEO CPU. It displays the location of interna

UM018809-0611 Address SpaceZNEO® CPU CoreUser Manual17To determine the amount of internal RAM and internal nonvolatile memory available for the spec

Address Space UM018809-061118ZNEO® CPU CoreUser ManualThe ZNEO CPU assembler provides a configurable address range mnemonic (RAM) that can be speci

UM018809-0611 Address SpaceZNEO® CPU CoreUser Manual19EndiannessThe ZNEO CPU accesses data in Big Endian order; which means the address of a multi-b

Address Space UM018809-061120ZNEO® CPU CoreUser ManualFigure 5. Alignment of 16-Bit and 32-Bit Operations on 16-Bit MemoriesMSBLSBFF_0080H FF_0081H

UM018809-0611 Assembly Language IntroductionZNEO® CPU CoreUser Manual21Assembly Language IntroductionAssembly language uses mnemonic symbols to repr

Assembly Language Introduction UM018809-061122ZNEO® CPU CoreUser Manual ; in data (RAM space) memoryStr_Data: ; Make Str_Data label equal to curr

UM018809-0611 Assembly Language IntroductionZNEO® CPU CoreUser Manual23•Load•CPU Control•Program ControlTables 6 through 12 list the instructions f

Revision History UM018809-0611ivZNEO® CPU CoreUser ManualJan 200603 Multiple Updated ZNEO trademark. All02 Instruction Opcodes Moved opcodes beginn

Assembly Language Introduction UM018809-061124ZNEO® CPU CoreUser ManualTable 8. Bit Manipulation Instructions Mnemonic Operands Instruction PageTCM

UM018809-0611 Assembly Language IntroductionZNEO® CPU CoreUser Manual25Table 11. CPU Control Instructions Mnemonic Operands Instruction PageATM — At

Assembly Language Introduction UM018809-061126ZNEO® CPU CoreUser Manual

UM018809-0611 Operand AddressingZNEO® CPU CoreUser Manual27Operand AddressingMost ZNEO CPU instructions operate on one or two registers, or one regi

Operand Addressing UM018809-061128ZNEO® CPU CoreUser ManualImmediate DataAn Immediate Data operand specifies a source value to be used directly by

UM018809-0611 Operand AddressingZNEO® CPU CoreUser Manual29Direct Memory AddressingA Direct Memory operand specifies a memory address to be used by

Operand Addressing UM018809-061130ZNEO® CPU CoreUser ManualThe ERAM and EROM address space suffixes tell the assembler to use 32-bit addressing, as

UM018809-0611 Operand AddressingZNEO® CPU CoreUser Manual31 Resizing DataWhen an 8-bit or 16-bit memory location is written, the value from the sour

Operand Addressing UM018809-061132ZNEO® CPU CoreUser Manual LD.SB R10,7002HBy default, the ZNEO CPU assembler uses an unsigned instruction opcode

UM018809-0611 Operand AddressingZNEO® CPU CoreUser Manual33 Depending on the instruction, register-indirect addressing can be used for either the so

UM018809-0611 Table of ContentsZNEO® CPU CoreUser ManualvTable of ContentsRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operand Addressing UM018809-061134ZNEO® CPU CoreUser Manualis not necessary. The ZNEO® CPU assembler automatically uses a shorter LD opcode if poss

UM018809-0611 Operand AddressingZNEO® CPU CoreUser Manual35If the required offset for a PC-based instruction exceeds the allowed range, the assemble

Operand Addressing UM018809-061136ZNEO® CPU CoreUser ManualUsing the Stack Pointer (R15)Stack operations are a special kind of register-indirect me

UM018809-0611 Operand AddressingZNEO® CPU CoreUser Manual37The PUSHM and POPM instructions always push or pop all 32 bits of each register. The ZNEO

Operand Addressing UM018809-061138ZNEO® CPU CoreUser ManualThis leaves the value FFFF_FF50H in register R15. Figure 9 displays how this example cle

UM018809-0611 Operand AddressingZNEO® CPU CoreUser Manual39This leaves R15 unchanged, but sets the Z flag as R15[2] is clear. The TCM instruction (T

Operand Addressing UM018809-061140ZNEO® CPU CoreUser ManualRelative Address. The JP, JP cc, or CALL opcode includes a signed relative offset field

UM018809-0611 InterruptsZNEO® CPU CoreUser Manual41InterruptsPeripherals use an interrupt request (IRQ) signal to get the CPU’s attention when it ne

Interrupts UM018809-061142ZNEO® CPU CoreUser ManualMaster Interrupt Enable flag (IRQE) in the FLAGS register in I/O memory. It is possible to enable

UM018809-0611 InterruptsZNEO® CPU CoreUser Manual43Example. Figure 11 displays an example of addresses used during an interrupt operation. In this e

Table of Contents UM018809-0611viZNEO® CPU CoreUser ManualOperand Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupts UM018809-061144ZNEO® CPU CoreUser ManualReturning From a Vectored InterruptIf no interrupts are pending or the Chained Interrupt Enable F

UM018809-0611 InterruptsZNEO® CPU CoreUser Manual456. Pop the Flags register, including the Master Interrupt Enable bit (IRQE), from the stack. This

Interrupts UM018809-061146ZNEO® CPU CoreUser Manual2. Configure the Interrupt Enable Registers to disable lower priority interrupts.3. Execute an EI

UM018809-0611 InterruptsZNEO® CPU CoreUser Manual47Polling is performed in a frequently-executed section of code, such as the main loop of an intera

Interrupts UM018809-061148ZNEO® CPU CoreUser Manual

UM018809-0611 System ExceptionsZNEO® CPU CoreUser Manual49System ExceptionsSystem exceptions are similar to Vectored Interrupts; however, exceptions

System Exceptions UM018809-061150ZNEO® CPU CoreUser ManualProgram Counter OverflowThe Program Counter Overflow exception can be used to restrict pr

UM018809-0611 System ExceptionsZNEO® CPU CoreUser Manual51Observe the following steps to set up Stack Overflow Protection.1. Initialize the Stack Po

System Exceptions UM018809-061152ZNEO® CPU CoreUser ManualFor more information about the System Exception register (SYSEXCP), refer to the ZNEO pro

UM018809-0611 Software TrapsZNEO® CPU CoreUser Manual53Software TrapsThe TRAP Vector instruction allows software to invoke any vectored service rout

UM018809-0611 Table of ContentsZNEO® CPU CoreUser ManualviiADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Software Traps UM018809-061154ZNEO® CPU CoreUser Manual

UM018809-0611 Instruction OpcodesZNEO® CPU CoreUser Manual55Instruction OpcodesThis chapter provides a complete list of ZNEO CPU instruction opcodes

Instruction Opcodes UM018809-061156ZNEO® CPU CoreUser ManualTable 18 lists instructions by opcode. Unimplemented opcodes are shaded in grey.Table 1

UM018809-0611 Instruction OpcodesZNEO® CPU CoreUser Manual570000 0000 0010 dddd 0xrr rrrr rrrr rrrrLD Rd, soff14(PC) Load Quad pointed to by program

Instruction Opcodes UM018809-061158ZNEO® CPU CoreUser Manual0000 0011 1111 ssssaaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaaLD addr32, Rs Store memory Qu

UM018809-0611 Instruction OpcodesZNEO® CPU CoreUser Manual590001 001+ ssss dddd LD Rd, (Rs)LD Rd, (Rs++)Load dst register from Quad with optional Po

Instruction Opcodes UM018809-061160ZNEO® CPU CoreUser Manual0100 1000 ssss dddd1xrr rrrr rrrr rrrrLEA Rd, soff14(Rs) Load dst with effective addres

UM018809-0611 Instruction OpcodesZNEO® CPU CoreUser Manual610111 0ooo 1100 ddddaaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaaBOP Rd, addr32 Binary operatio

Instruction Opcodes UM018809-061162ZNEO® CPU CoreUser Manual1010 1011 1ooo ddddiiii iiii iiii iiii iiii iiii iiii iiiiBOP (Rd), #imm32 Binary opera

UM018809-0611 Instruction OpcodesZNEO® CPU CoreUser Manual631011 0110 ssss dddd SLL Rd, Rs Logical shift left by src bits. Extend modifier causes sh

Table of Contents UM018809-0611viiiZNEO® CPU CoreUser ManualPUSHMHI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Instruction Opcodes UM018809-061164ZNEO® CPU CoreUser Manual1111 01xx xxxx xxxx — Unimplemented1111 10xx xxxx xxxx — Unimplemented1111 1100 xxxx xx

UM018809-0611 Instruction Set ReferenceZNEO® CPU CoreUser Manual65Instruction Set ReferenceThis chapter provides detailed description of the assembl

Instruction Set Reference UM018809-061166ZNEO® CPU CoreUser ManualMiscellaneous AbbreviationsTable 20 lists additional symbols used in the instruct

UM018809-0611 MnemonicZNEO® CPU CoreUser Manual67Example DescriptionThe instruction sets described on the following pages are organized alphabetical

ADC Instruction UM018809-061168ZNEO® CPU CoreUser ManualADCDefinitionAdd with CarrySyntax ADC dst, srcOperationdstdst + src + C DescriptionThe s

UM018809-0611 ADC InstructionZNEO® CPU CoreUser Manual69Syntax and OpcodesInstruction, OperandsExtendPrefix Word 0 Word 1 Word 2ADC Rd, #imm32 0007

ADC Instruction UM018809-061170ZNEO® CPU CoreUser ManualExamplesBefore: R3=16H, R11=20H, Flag C=1ADC R3, R11 ;Object Code: 0007 A0B3After: R3=37H,

UM018809-0611 ADD InstructionZNEO® CPU CoreUser Manual71ADDDefinitionAddSyntaxADD dst, srcOperationdstdst + srcDescriptionAdd the source operand

ADD Instruction UM018809-061172ZNEO® CPU CoreUser ManualSyntax and OpcodesInstruction, Operands Word 0 Word 1 Word 2ADD Rd, #imm32 {AA8H, Rd} imm[3

UM018809-0611 ADD InstructionZNEO® CPU CoreUser Manual73ExamplesBefore: R3=16H, R11=20HADD R3, R11 ;Object Code: A0B3After: R3=36H, Flags C, Z, S, V

UM018809-0611 List of FiguresZNEO® CPU CoreUser ManualixList of FiguresFigure 1. ZNEO CPU Block Diagram . . . . . . . . . . . . . . . . . . . . .

AND Instruction UM018809-061174ZNEO® CPU CoreUser ManualANDDefinitionLogical ANDSyntaxAND dst, srcOperationdstdst AND src DescriptionThe source

UM018809-0611 AND InstructionZNEO® CPU CoreUser Manual75Flags are set based on the memory destination size, or 32 bits for register destinations.Syn

AND Instruction UM018809-061176ZNEO® CPU CoreUser ManualExamplesBefore: R1[7:0]=38H (0011_1000B), R14[7:0]=8DH (1000_1101B)AND R1, R14 ;Object Code

UM018809-0611 ATM InstructionZNEO® CPU CoreUser Manual77ATMDefinitionAtomic ExecutionSyntaxATMOperationBlock all interrupt and DMA requests during e

BRK Instruction UM018809-061178ZNEO® CPU CoreUser ManualBRKDefinitionOn-Chip Debugger BreakSyntaxBRKOperationNoneDescriptionIf the Break capability

UM018809-0611 CALL InstructionZNEO® CPU CoreUser Manual79CALLDefinitionCALL ProcedureSyntaxCALL dstOperationSPSP4(SP)PCPCdestination addr

CALL Instruction UM018809-061180ZNEO® CPU CoreUser ManualExampleBefore: PC=0000_0472H, SP=FFFF_DE24H, R7=0000_3521HCALL (R7) ;Object Code: F217Afte

UM018809-0611 CALLA InstructionZNEO® CPU CoreUser Manual81CALLADefinitionCALL AbsoluteSyntaxCALLA dstOperationSP  SP – 4(SP)  PCPC  dstDescript

CLR Instruction UM018809-061182ZNEO® CPU CoreUser ManualCLRDefinitionClear SyntaxCLR dstOperationdst  0DescriptionAll bits of the destination oper

UM018809-0611 CLR InstructionZNEO® CPU CoreUser Manual83ExamplesBefore: FFFF_B032H=8BF7_47AFHCLR B032H:RAM ;Object code: ADA8 B032 or ADAE B032After