Zilog Z16C30 Manuel d'utilisateur télécharger pdf (Page 156)

8-1

Z16C30 USC

USER'S MANUAL

ZILOG

UM97USC0100

8.1 INTRODUCTION

SER

’s M

ANUAL

CHAPTER 8

SOFTWARE SUMMARY

This chapter includes a bit by bit description of all the

registers in the IUSC.

8.2 ABOUT RESETTING

The USC is placed in an initial inactive state whenever

external hardware drives the /RESET pin low. In this state,

it stores the next data written to it in the Bus Configuration

ware uses for the write operation. Chapter 2 describes how

the address used for the BCR write is actually important, in

the sense that the address line connected to the A//B pin

(the one used for channel selection in normal operation)

determines whether the USC drives and receives the

/WAIT//RDY pin as a “wait” or “acknowledge” handshake.

Aside from requiring the BCR write, software can reset a

channel just as thoroughly and completely as a hardware

reset does. 'Resetting a Channel' in Chapter 5 describes

how to do this, by first writing a 1 to the RTReset bit in the

Channel Command/Address Register (CCAR10), and then

writing zeroes to the whole CCAR.

After either a hardware or a software reset, all register bits

in the USC are zero except for the following:

1. The following bits reflect the state of pins. The USC

treats these as inputs until and unless software pro-

grams them as outputs.

MISR14 /RxC

MISR12 /TxC

MISR10 /RxREQ

MISR8 /TxREQ

MISR6 /DCD

MISR4 /CTS

CCSR1 /TxACK

CCSR0 /RxACK

2. The following bits are 1 because the TxFIFO is empty:

TCSR0 TxEmpty

TICR13 (indicates 32 empty entries)

UM009402-0201

1 2 ... 151 152 153 154 155 156 157 158 159 160 161 ... 207 208

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Zilog Z16C30 Manuel d'utilisateur Page 156

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