Zilog Z16C35 Manuel d'utilisateur télécharger pdf (Page 131)

ISCC

User Manual

UM011002-0808

125

Bit 0 is the All Sent status

In Asynchronous mode, this bit is set when all characters have completely cleared the

transmitter pins. Most modems contain additional delays in the data path, which requires

the modem control signals to remain active until after the data has cleared both the trans-

mitter and the modem. This bit is always set in synchronous and SDLC modes.

5.5.3 Read Register 2

RR2 contains the interrupt vector written into WR2. When the register is accessed in

Channel A, the vector returned is the vector actually stored in WR2. When this register is

accessed in Channel B, the vector returned includes status information in bits 1, 2 and 3 or

in bits 6, 5 and 4, depending on the state of the Status High/Status Low bit in WR9 and

independent of the state of the VIS bit in WR9. The vector is modified according to Table

5-7 shown in the explanation of the VIS bit in WR9. If no interrupts are pending the status

is V3,V2,V1 -011, or V6,V5,V4-110. Figure 5-20 shows the bit positions for RR2.

1 1 1 1 8

0 0 0 2 8

Table 5–35. Bits per Character Residue Decoding

Bits per Character Bit 3 Bit 2 Bit 1

8 0 1 1

7 0 0 0

6 0 1 0

5001

Table 5–34. I-Field Bit Selection (8 Bits Only) (Continued)

Bit 3 Bit 2 Bit 1

I-Field Bits

in Last Byte

I-Field Bits

in Previous Byte

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Zilog Z16C35 Manuel d'utilisateur Page 131