Zilog eZ80F92 Manuel d'utilisateur télécharger pdf (Page 20)

eZ80F92 Development Kit

User Manual

eZ80Acclaim!

Development Platform UM013911-0607

46 RD Bidirectional Low Yes

47 WR

Bidirectional Low Yes

48 INSTRD

Input Low Yes

49 BUSACK

Input Pull-Up 10 KΩ; Low Yes

50 BUSREQ

Output Pull-Up 10 KΩ; Low Yes

Table 2. eZ80Acclaim!

Development Platform

Peripheral Bus Connector Identification—JP1* (Continued)

Pin # Symbol Signal Direction Active Level eZ80F92 Signal

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from

this table. The entire interface is represented in the eZ80F92 Module Schematics on pages 65

through 67.

2. The Power and Ground nets are connected directly to the eZ80F92 device.

3. External capacitive loads on RD

, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF

to satisfy the timing requirements for the eZ80

CPU. All unused inputs should be pulled to

either V

or GND, depending on their inactive levels to reduce power consumption and to

reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in

the eZ80F92’s Peripheral Power-Down Register.

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 86 87

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Zilog eZ80F92 Manuel d'utilisateur Page 20