Zilog Z08470 Manuel d'utilisateur

Copyright ©2015 Zilog, Inc. All rights reserved.www.zilog.comUM008007-0715User ManualZ80 MicroprocessorsZ80 CPU

UM008007-0715 List of FiguresZ80 CPUUser ManualxList of FiguresFigure 1. Z80 CPU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z80 Instruction Set UM008007-071588Z80 CPUUser ManualLD A, (nn)OperationA ← (nn)Op CodeLDOperandsA, (nn)DescriptionThe contents of the memory locati

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual89LD (BC), AOperation(BC) ← AOp CodeLDOperands(BC), ADescriptionThe contents of the Accum

Z80 Instruction Set UM008007-071590Z80 CPUUser ManualLD (DE), AOperation(DE) ← AOp CodeLDOperands(DE), ADescriptionThe contents of the Accumulator a

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual91LD (nn), AOperation(nn) ← AOp CodeLDOperands(nn), ADescriptionThe contents of the Accum

Z80 Instruction Set UM008007-071592Z80 CPUUser ManualLD A, IOperationA ← 1Op CodeLDOperandsA, IDescriptionThe contents of the Interrupt Vector Regis

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual93LD A, ROperationA ← ROp CodeLDOperandsA, RDescriptionThe contents of Memory Refresh Reg

Z80 Instruction Set UM008007-071594Z80 CPUUser ManualLD I,AOperationI ← AOp CodeLDOperandsI, ADescriptionThe contents of the Accumulator are loaded

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual95LD R, AOperationR ← AOp CodeLDOperandsR, ADescriptionThe contents of the Accumulator ar

Z80 Instruction Set UM008007-071596Z80 CPUUser Manual16-Bit Load GroupThe following 16-bit load instructions are each described in this section. Sim

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual97LD dd, nnOperationdd ← nnOp CodeLDOperandsdd, nnDescriptionThe 2-byte integer nn is loa

List of Figures UM008007-0715xiZ80 CPUUser ManualFigure 29. Extended Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z80 Instruction Set UM008007-071598Z80 CPUUser ManualLD IX, nnOperationIX ← nnOp CodeLDOperandsIX, nnDescriptionThe n integer is loaded to Index Reg

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual99LD IY, nnOperationIY ← nnOp CodeLDOperandsIY, nnDescriptionThe nn integer is loaded to

Z80 Instruction Set UM008007-0715100Z80 CPUUser ManualLD HL, (nn)OperationH ← (nn + 1), L ← (nn)Op CodeLDOperandsHL, (nn)DescriptionThe contents of

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual101LD dd, (nn)Operationddh ← (nn + 1) ddl ← (nn)Op CodeLDOperandsdd, (nn)DescriptionThe c

Z80 Instruction Set UM008007-0715102Z80 CPUUser ManualExampleIf Address 2130h contains 65h and address 2131h contains 78h, then upon the execution o

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual103LD IX, (nn)OperationIXh ← (nn + 1), IXI ← (nn)Op CodeLDOperandsIX, (nn)DescriptionThe

Z80 Instruction Set UM008007-0715104Z80 CPUUser ManualLD IY, (nn)OperationIYh ← (nn + 1), IYI ← nn)Op CodeLDOperandsIY, (nn)DescriptionThe contents

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual105LD (nn), HLOperation(nn + 1) ← H, (nn) ← LOp CodeLDOperands(nn), HLDescriptionThe con

Z80 Instruction Set UM008007-0715106Z80 CPUUser ManualLD (nn), ddOperation(nn + 1) ← ddh, (nn) ← ddlOp CodeLDOperands(nn), ddDescriptionThe low-ord

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual107ExampleIf register pair BC contains the number 4644h, the instruction LD (1000h), BC r

UM008007-0715 List of TablesZ80 CPUUser ManualxiiList of TablesTable 1. Interrupt Enable/Disable, Flip-Flops . . . . . . . . . . . . . . . . . . .

Z80 Instruction Set UM008007-0715108Z80 CPUUser ManualLD (nn), IXOperation(nn + 1) ← IXh, (nn) ← IXIOp CodeLDOperands(nn), IXDescriptionThe low-ord

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual109LD (nn), IYOperation(nn + 1) ← IYh, (nn) ← IYIOp CodeLDOperands(nn), IYDescriptionThe

Z80 Instruction Set UM008007-0715110Z80 CPUUser ManualLD SP, HLOperationSP ← HLOp CodeLDOperandsSP, HLDescriptionThe contents of the register pair H

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual111LD SP, IXOperationSP ← IXOp CodeLDOperandsSP, IXDescriptionThe 2-byte contents of Inde

Z80 Instruction Set UM008007-0715112Z80 CPUUser ManualLD SP, IYOperationSP ← IYOp CodeLDOperandsSP, IYDescriptionThe 2-byte contents of Index Regist

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual113PUSH qqOperation(SP – 2) ← qqL, (SP – 1) ← qqHOp CodePUSHOperandqqDescriptionThe conte

Z80 Instruction Set UM008007-0715114Z80 CPUUser ManualExampleIf the AF Register pair contains 2233h and the Stack Pointer contains 1007h, then upon

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual115PUSH IXOperation(SP – 2) ← IXL, (SP – 1) ← IXHOp CodePUSHOperandIXDescriptionThe conte

Z80 Instruction Set UM008007-0715116Z80 CPUUser ManualPUSH IYOperation(SP – 2) ← IYL, (SP – 1) ← IYHOp CodePUSHOperandIYDescriptionThe contents of I

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual117POP qqOperationqqH ← (SP+1), qqL ← (SP)Op CodePOPOperandqqDescriptionThe top two bytes

UM008007-0715 Architectural OverviewZ80 CPUUser Manual1Architectural OverviewZilog’s Z80 CPU family of components are fourth-generation enhanced mic

Z80 Instruction Set UM008007-0715118Z80 CPUUser ManualExampleIf the Stack Pointer contains 1000h, memory location 1000h contains 55h, and location 1

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual119POP IXOperationIXH ← (SP+1), IXL ← (SP)Op CodePOPOperandIXDescriptionThe top two bytes

Z80 Instruction Set UM008007-0715120Z80 CPUUser ManualPOP IYOperationIYH ← (SP – X1), IYL ← (SP)Op CodePOPOperandIYDescriptionThe top two bytes of t

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual121Exchange, Block Transfer, and Search GroupThe following exchange, block transfer, and

Z80 Instruction Set UM008007-0715122Z80 CPUUser ManualEX DE, HLOperationDE ↔ HLOp CodeEXOperandsDE, HLDescriptionThe 2-byte contents of register pai

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual123EX AF, AF′OperationAF ↔ AF'Op CodeEXOperandsAF, AF′DescriptionThe 2-byte contents

Z80 Instruction Set UM008007-0715124Z80 CPUUser ManualEXXOperation(BC) ↔ (BC′), (DE) ↔ (DE'), (HL) ↔ (HL′)Op CodeEXXOperandsNone.DescriptionEac

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual125EX (SP), HLOperationH ↔ (SP+1), L ↔ (SP)Op CodeEXOperands(SP), HLDescriptionThe low-or

Z80 Instruction Set UM008007-0715126Z80 CPUUser ManualEX (SP), IXOperationIXH ↔ (SP+1), IXL ↔ (SP)Op CodeEXOperands(SP), IXDescriptionThe low-order

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual127EX (SP), IYOperationIYH ↔ (SP+1), IYL ↔ (SP)Op CodeEXOperands(SP), IYDescriptionThe lo

Architectural Overview UM008007-07152Z80 CPUUser ManualCPU RegisterThe Z80 CPU contains 208 bits of read/write memory that are available to the prog

Z80 Instruction Set UM008007-0715128Z80 CPUUser ManualLDIOperation(DE) ← (HL), DE ← DE + 1, HL ← HL + 1, BC ← BC – 1Op CodeLDIOperands(SP), HLDescri

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual129register pair contains 7h, then the instruction LDI results in the following contents

Z80 Instruction Set UM008007-0715130Z80 CPUUser ManualLDIROperation(DE) ← (HL), DE ← DE + 1, HL ← HL + 1, BC F ↔ BC – 1Op CodeLDIROperandB8Descripti

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual131P/V is reset.N is reset.C is not affected.ExampleThe HL register pair contains 11111h,

Z80 Instruction Set UM008007-0715132Z80 CPUUser ManualLDDOperation(DE) ← (HL), DE ← DE – 1, HL ← HL– 1, BC ← BC– 1Op CodeLDDOperandsNone.Description

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual133ister pair contains 7h, then instruction LDD results in the following contents in regi

Z80 Instruction Set UM008007-0715134Z80 CPUUser ManualLDDROperation(DE) ← (HL), DE ← D ← 1, HL ← HL– 1, BC ← BC – 1Op CodeLDDROperandsNone.Descripti

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual135Condition Bits AffectedS is not affected.Z is not affected.H is reset.P/V is reset.N i

Z80 Instruction Set UM008007-0715136Z80 CPUUser ManualCPIOperationA – (HL), HL ← HL +1, BC ← BC – 1Op CodeCPIOperandsNone.DescriptionThe contents of

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual137CPIROperationA – (HL), HL ← HL+1, BC ← BC – 1Op CodeCPIROperandsNone.DescriptionThe co

UM008007-0715 General Purpose RegistersZ80 CPUUser Manual3Two Index Registers (IX and IY). The two independent index registers hold a 16-bit base ad

Z80 Instruction Set UM008007-0715138Z80 CPUUser ManualCondition Bits AffectedS is set if result is negative; otherwise, it is reset.Z is set if A eq

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual139CPDOperationA – (HL), HL ← HL – 1, BC ← BC – 1Op CodeCPDOperandsNone.DescriptionThe co

Z80 Instruction Set UM008007-0715140Z80 CPUUser ManualCPDROperationA – (HL), HL ← HL – 1, BC ← BC – 1Op CodeCPDROperandsNone.DescriptionThe contents

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual141P/V is set if BC – 1 ≠ 0; otherwise, it is reset.N is set.C is not affected.ExampleThe

Z80 Instruction Set UM008007-0715142Z80 CPUUser Manual8-Bit Arithmetic GroupThe following 8-bit arithmetic group instructions are each described in

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual143ADD A, rOperationA ← A + rOp CodeADDOperandsA, rDescriptionThe contents of register r

Z80 Instruction Set UM008007-0715144Z80 CPUUser ManualP/V is set if overflow; otherwise, it is reset.N is reset.C is set if carry from bit 7; otherw

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual145ADD A, nOperationA ← A + nOp CodeADDOperandsA, nDescriptionThe n integer is added to t

Z80 Instruction Set UM008007-0715146Z80 CPUUser ManualADD A, (HL)OperationA ← A + (HL)Op CodeADDOperandsA, (HL)DescriptionThe byte at the memory add

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual147ADD A, (IX + d)OperationA ← A + (IX+d)Op CodeADDOperandsA, (IX + d)DescriptionThe cont

Architectural Overview UM008007-07154Z80 CPUUser Manualisters are used for a wide range of applications. They also simplify programing, specifi-call

Z80 Instruction Set UM008007-0715148Z80 CPUUser ManualADD A, (IY + d)OperationA ← A + (IY+d)Op CodeADDOperandsA, (IY + d)DescriptionThe contents of

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual149ADC A, sOperationA ← A + s + CYOp CodeADCOperandsA, sThis s operand is any of r, n, (H

Z80 Instruction Set UM008007-0715150Z80 CPUUser Manualr identifies registers B, C, D, E, H, L, or A, assembled as follows in the object code field:D

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual151SUB sOperationA ← A – sOp CodeSUBOperandsThis s operand is any of r, n, (HL), (IX+d),

Z80 Instruction Set UM008007-0715152Z80 CPUUser Manualr identifies registers B, C, D, E, H, L, or A assembled as follows in the object code field:De

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual153SBC A, sOperationA ← A – s – CYOp CodeSBCOperandsA, sThe s operand is any of r, n, (HL

Z80 Instruction Set UM008007-0715154Z80 CPUUser Manualr identifies registers B, C, D, E, H, L, or A assembled as follows in the object code field:De

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual155AND sOperationA ← A ˄ sOp CodeANDOperandsThe s operand is any of r, n, (HL), (IX+d), o

Z80 Instruction Set UM008007-0715156Z80 CPUUser Manualr identifies registers B, C, D, E, H, L, or A specified in the assembled object code field, as

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual157OR sOperationA ← A ˅ s Op CodeOROperandsThe s operand is any of r, n, (HL), (IX+d), or

UM008007-0715 Pin FunctionsZ80 CPUUser Manual5Pin FunctionsA15–A0. Address Bus (output, active High, tristate). A15–A0 form a 16-bit Address Bus, wh

Z80 Instruction Set UM008007-0715158Z80 CPUUser Manualr identifies registers B, C–, D, E, H, L, or A specified in the assembled object code field, a

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual159XOR sOperationA ← A  s Op CodeXOROperandsThe s operand is any of r, n, (HL), (IX+d),

Z80 Instruction Set UM008007-0715160Z80 CPUUser Manualr identifies registers B, C, D, E, H, L, or A specified in the assembled object code field, as

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual161CP sOperationA – sOp CodeCPOperandsThe s operand is any of r, n, (HL), (IX+d), or (lY+

Z80 Instruction Set UM008007-0715162Z80 CPUUser Manualr identifies registers B, C, D, E, H, L, or A specified in the assembled object code field, as

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual163INC rOperationr ← r + 1Op CodeINCOperandrDescriptionRegister r is incremented and regi

Z80 Instruction Set UM008007-0715164Z80 CPUUser ManualN is reset.C is not affected.ExampleIf the D Register contains 28h, then upon the execution of

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual165INC (HL)Operation(HL) ← (HL) + 1Op CodeINCOperand(HL)DescriptionThe byte contained in

Z80 Instruction Set UM008007-0715166Z80 CPUUser ManualINC (IX+d)Operation(IX+d) ← (IX+d) + 1Op CodeINCOperands(IX+d)DescriptionThe contents of Index

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual167INC (IY+d)Operation(lY+d) ← (lY+d) + 1Op CodeINCOperands(lY+d)DescriptionThe contents

Architectural Overview UM008007-07156Z80 CPUUser ManualRD, and WR have entered their high-impedance states. The external circuitry can now control t

Z80 Instruction Set UM008007-0715168Z80 CPUUser ManualDEC mOperationm ← m – 1Op CodeDECOperandmThe m operand is any of r, (HL), (IX+d), or (lY+d), a

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual169DescriptionThe byte specified by the m operand is decremented.Condition Bits AffectedS

Z80 Instruction Set UM008007-0715170Z80 CPUUser ManualGeneral-Purpose Arithmetic and CPU Control GroupsThe following general-purpose arithmetic and

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual171DAAOperation@Op CodeDAAOperandsNone.DescriptionThis instruction conditionally adjusts

Z80 Instruction Set UM008007-0715172Z80 CPUUser ManualCondition Bits AffectedS is set if most-significant bit of the Accumulator is 1 after an opera

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual173CPLOperationA ← AOp CodeCPLOperandsNone.DescriptionThe contents of the Accumulator (Re

Z80 Instruction Set UM008007-0715174Z80 CPUUser ManualNEGOperationA ← 0 – AOp CodeNEGOperandsNone.DescriptionThe contents of the Accumulator are neg

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual175ExampleThe Accumulator contains the following data:Upon the execution of a NEG instruc

Z80 Instruction Set UM008007-0715176Z80 CPUUser ManualCCFOperationCY ← CYOp CodeCCFOperandsNone.DescriptionThe Carry flag in the F Register is inver

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual177SCFOperationCY ← 1Op CodeSCFOperandsNone.DescriptionThe Carry flag in the F Register i

UM008007-0715 TimingZ80 CPUUser Manual7RFSH. Refresh (output, active Low). RFSH, together with MREQ, indicates that the lower seven bits of the syst

Z80 Instruction Set UM008007-0715178Z80 CPUUser ManualNOPOperation—Op CodeNOPOperandsNone.DescriptionThe CPU performs no operation during this machi

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual179HALTOperation—Op CodeHALTOperandsNone.DescriptionThe HALT instruction suspends CPU ope

Z80 Instruction Set UM008007-0715180Z80 CPUUser ManualDIOperationIFF ← 0Op CodeDIOperandsNone.DescriptionDI disables the maskable interrupt by reset

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual181EIOperationIFF ← 1Op CodeEIOperandsNone.DescriptionThe enable interrupt instruction se

Z80 Instruction Set UM008007-0715182Z80 CPUUser ManualIM 0OperationSet Interrupt Mode 0Op CodeIMOperand0DescriptionThe IM 0 instruction sets Interru

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual183IM 1OperationSet Interrupt Mode 1Op CodeIMOperand1DescriptionThe IM 1 instruction sets

Z80 Instruction Set UM008007-0715184Z80 CPUUser ManualIM 2OperationSet Interrupt Mode 2Op CodeIMOperand2DescriptionThe IM 2 instruction sets the vec

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual18516-Bit Arithmetic GroupThe following 16-bit arithmetic group instructions are each des

Z80 Instruction Set UM008007-0715186Z80 CPUUser ManualADD HL, ssOperationHL ← HL + ssOp CodeADDOperandsHL, ssDescriptionThe contents of register pai

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual187C is set if carry from bit 15; otherwise, it is reset.ExampleIf register pair HL conta

UM008007-0715iiZ80 CPUUser ManualDO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.LIFE SUPPORT POLICYZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CR

Architectural Overview UM008007-07158Z80 CPUUser ManualWAIT state is entered during the following cycle. Using this technique, the read can be lengt

Z80 Instruction Set UM008007-0715188Z80 CPUUser ManualADC HL, ssOperationHL ← HL + ss + CYOp CodeADCOperandsHL, ssDescriptionThe contents of registe

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual189N is reset.C is set if carry from bit 15; otherwise, it is reset.ExampleIf register pa

Z80 Instruction Set UM008007-0715190Z80 CPUUser ManualSBC HL, ssOperationHL ← HI – ss – CYOp CodeSBCOperandsHL, ssDescriptionThe contents of the reg

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual191N is set.C is set if borrow; otherwise, it is reset.ExampleIf the HL register pair con

Z80 Instruction Set UM008007-0715192Z80 CPUUser ManualADD IX, ppOperationIX ← IX + ppOp CodeADDOperandsIX, ppDescriptionThe contents of register pai

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual193N is reset.C is set if carry from bit 15; otherwise, it is reset.ExampleIf Index Regis

Z80 Instruction Set UM008007-0715194Z80 CPUUser ManualADD IY, rrOperationIY ← IY + rrOp CodeADDOperandsIY, rrDescriptionThe contents of register pai

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual195N is reset.C is set if carry from bit 15; otherwise, it is reset.ExampleIf Index Regis

Z80 Instruction Set UM008007-0715196Z80 CPUUser ManualINC ssOperationss ← ss + 1Op CodeINCOperandssDescriptionThe contents of register pair ss (any

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual197INC IXOperationIX ← IX + 1Op CodeINCOperandIXDescriptionThe contents of Index Register

UM008007-0715 Memory Read Or WriteZ80 CPUUser Manual9Memory Read Or WriteFigure 6 shows the timing of memory read or write cycles other than an op c

Z80 Instruction Set UM008007-0715198Z80 CPUUser ManualINC IYOperationIY ← IY + 1Op CodeINCOperandIYDescriptionThe contents of Index Register IY are

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual199DEC ssOperationss ← ss – 1Op CodeDECOperandssDescriptionThe contents of register pair

Z80 Instruction Set UM008007-0715200Z80 CPUUser ManualDEC IXOperationIX ← IX – 1Op CodeDECOperandIXDescriptionThe contents of Index Register IX are

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual201DEC IYOperationIY ← IY– 1Op CodeDECOperandIYDescriptionThe contents of Index Register

Z80 Instruction Set UM008007-0715202Z80 CPUUser ManualRotate and Shift GroupThe following rotate and shift group instructions are each described in

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual203RLCAOperationOp CodeRLCAOperandsNone.DescriptionThe contents of the Accumulator (Regis

Z80 Instruction Set UM008007-0715204Z80 CPUUser ManualExampleThe Accumulator contains the following data:Upon the execution of an RLCA instruction,

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual205RLAOperationOp CodeRLAOperandsNone.DescriptionThe contents of the Accumulator (Registe

Z80 Instruction Set UM008007-0715206Z80 CPUUser ManualExampleThe Accumulator and the Carry flag contains the following data:Upon the execution of an

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual207RRCAOperationOp CodeRRCAOperandsNone.DescriptionThe contents of the Accumulator (Regis

Architectural Overview UM008007-071510Z80 CPUUser ManualInput or Output CyclesFigure 7 shows an I/O read or I/O write operation. During I/O operatio

Z80 Instruction Set UM008007-0715208Z80 CPUUser ManualUpon the execution of an RRCA instruction, the Accumulator and the Carry flag now con-tain:00

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual209RRAOperationOp CodeRRAOperandsNone.DescriptionThe contents of the Accumulator (Registe

Z80 Instruction Set UM008007-0715210Z80 CPUUser ManualExampleThe Accumulator and the Carry Flag contain the following data:Upon the execution of an

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual211RLC rOperationOp CodeRLCOperandrDescriptionThe contents of register r are rotated left

Z80 Instruction Set UM008007-0715212Z80 CPUUser ManualCondition Bits AffectedS is set if result is negative; otherwise, it is reset.Z is set if resu

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual213RLC (HL)OperationOp CodeRLCOperand(HL)DescriptionThe contents of the memory address sp

Z80 Instruction Set UM008007-0715214Z80 CPUUser ManualExampleThe HL register pair contains 2828h and the contents of memory location 2828h are:Upon

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual215RLC (IX+d)OperationOp CodeRLCOperand(IX+d)DescriptionThe contents of the memory addres

Z80 Instruction Set UM008007-0715216Z80 CPUUser ManualC is data from bit 7 of source register.ExampleIndex Register IX contains 1000h and memory loc

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual217RLC (IY+d)OperationOp CodeRLCOperand(lY+d)DescriptionThe contents of the memory addres

UM008007-0715 Bus Request/Acknowledge CycleZ80 CPUUser Manual11*In Figure 7, TW is an automatically-inserted WAIT state.Bus Request/Acknowledge Cycl

Z80 Instruction Set UM008007-0715218Z80 CPUUser ManualC is data from bit 7 of source register.ExampleIndex Register IY contains 1000h and memory loc

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual219RL mOperationOp CodePLOperandmThe m operand is any of r, (HL), (IX+d), or (lY+d), as d

Z80 Instruction Set UM008007-0715220Z80 CPUUser Manualr identifies registers B, C, D, E, H, L, or A assembled as follows in the object code field:De

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual221Upon the execution of an RL D instruction, the D Register and the Carry flag now conta

Z80 Instruction Set UM008007-0715222Z80 CPUUser ManualRRC mOperationOp CodeRRCOperandmThe m operand is any of r, (HL), (IX+d), or (lY+d), as defined

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual223r identifies registers B, C, D, E, H, L, or A assembled as follows in the object code

Z80 Instruction Set UM008007-0715224Z80 CPUUser ManualUpon the execution of an RRC A instruction, Register A and the Carry flag now contain:001010 0

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual225RR mOperationOp CodeRROperandmThe m operand is any of r, (HL), (IX+d), or (lY+d), as d

Z80 Instruction Set UM008007-0715226Z80 CPUUser Manualr identifies registers B, C, D, E, H, L, or A assembled as follows in the object code field:De

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual227Upon the execution of an RR (HL) instruction, location 4343h and the Carry flag now co

Architectural Overview UM008007-071512Z80 CPUUser Manuallarge blocks of data are transferred under DMA control. During a bus request cycle, the CPU

Z80 Instruction Set UM008007-0715228Z80 CPUUser ManualSLA mOperationOp CodeSLAOperandmThe m operand is any of r, (HL), (IX+d), or (lY+d), as defined

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual229r identifies registers B, C, D, E, H, L, or A assembled as follows in the object code

Z80 Instruction Set UM008007-0715230Z80 CPUUser ManualUpon the execution of an SLA L instruction, Register L and the Carry flag now contain:01 0 100

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual231SRA mOperationOp CodeSRAOperandmThe m operand is any of r, (HL), (IX+d), or (lY+d), as

Z80 Instruction Set UM008007-0715232Z80 CPUUser Manualr identifies registers B, C, D, E, H, L, or A assembled as follows in the object code field:De

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual233Upon the execution of an SRA (IX+3h) instruction, memory location 1003h and the Carry

Z80 Instruction Set UM008007-0715234Z80 CPUUser ManualSRL mOperationOp CodeSRLOperandmThe operand m is any of r, (HL), (IX+d), or (lY+d), as defined

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual235r identifies registers B, C, D, E, H, L, or A.DescriptionThe contents of operand m are

Z80 Instruction Set UM008007-0715236Z80 CPUUser ManualRLDOperationOp CodeRLDOperandsDescriptionThe contents of the low-order four bits (bits 3, 2, 1

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual237P/V is set if the parity of the Accumulator is even after an operation; otherwise, it

UM008007-0715 Nonmaskable Interrupt ResponseZ80 CPUUser Manual13Nonmaskable Interrupt ResponseFigure 10 shows the request/acknowledge cycle for the

Z80 Instruction Set UM008007-0715238Z80 CPUUser ManualRRDOperationOp CodeRRDOperandsDescriptionThe contents of the low-order four bits (bits 3, 2, 1

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual239P/V is set if the parity of the Accumulator is even after an operation; otherwise, it

Z80 Instruction Set UM008007-0715240Z80 CPUUser ManualBit Set, Reset, and Test GroupThe following bit set, reset, and test group instructions are ea

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual241BIT b, rOperationZ ← rbOp CodeBITOperandsb, rDescriptionThis instruction tests bit b i

Z80 Instruction Set UM008007-0715242Z80 CPUUser ManualH is set.P/V is unknown.N is reset.C is not affected.ExampleIf bit 2 in Register B contains 0,

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual243BIT b, (HL)OperationZ ← (HL)bOp CodeBITOperandsb, (HL)DescriptionThis instruction test

Z80 Instruction Set UM008007-0715244Z80 CPUUser ManualZ is set if specified bit is 0; otherwise, it is reset.H is set.P/V is unknown.H is reset.C is

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual245BIT b, (IX+d)OperationZ ← (IX+d)bOp CodeBITOperandsb, (IX+d)DescriptionThis instructio

Z80 Instruction Set UM008007-0715246Z80 CPUUser ManualCondition Bits AffectedS is unknown.Z is set if specified bit is 0; otherwise, it is reset.H i

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual247BIT b, (IY+d)OperationZ ← (IY+d)bOp CodeBITOperandsb, (lY+d)DescriptionThis instructio

Architectural Overview UM008007-071514Z80 CPUUser ManualHALT ExitWhen a software HALT instruction is executed, the CPU executes NOPs until an interr

Z80 Instruction Set UM008007-0715248Z80 CPUUser ManualCondition Bits AffectedS is unknown.Z is set if specified bit is 0; otherwise, it is reset.H i

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual249SET b, rOperationrb ← 1Op CodeSETOperandsb, rDescriptionBit b in register r (any of re

Z80 Instruction Set UM008007-0715250Z80 CPUUser ManualExampleUpon the execution of a SET 4, A instruction, bit 4 in Register A is set. Bit 0 is the

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual251SET b, (HL)Operation(HL)b ← 1Op CodeSETOperandsb, (HL)DescriptionBit b in the memory l

Z80 Instruction Set UM008007-0715252Z80 CPUUser ManualExampleIf the HL register pair contains 3000h, then upon the execution of a SET 4, (HL) instru

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual253SET b, (IX+d)Operation(IX+d)b ← 1Op CodeSETOperandsb, (IX+d)DescriptionBit b in the me

Z80 Instruction Set UM008007-0715254Z80 CPUUser ManualSET b, (IY+d)Operation(IY + d) b ← 1Op CodeSETOperandsb, (IY + d)DescriptionBit b in the memor

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual255Condition Bits AffectedNone.ExampleIf Index Register IY contains 2000h, then upon the

Z80 Instruction Set UM008007-0715256Z80 CPUUser ManualRES b, mOperationsb ← 0Op CodeRESOperandsb, mThe b operand represents any bit (7 through 0) of

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual257DescriptionBit b in operand m is reset.Condition Bits AffectedNone.ExampleUpon the exe

UM008007-0715 Power-Down Acknowledge CycleZ80 CPUUser Manual15The HALT instruction is repeated during the memory cycle shown in Figure 11.Power-Down

Z80 Instruction Set UM008007-0715258Z80 CPUUser ManualJump GroupThe following jump group instructions are each described in this section. Simply cli

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual259JP nnOperationPC ← nnOp CodeJPOperandnnThe first operand in this assembled object code

Z80 Instruction Set UM008007-0715260Z80 CPUUser ManualJP cc, nnOperationIF cc true, PC ← nnOp CodeJPOperandscc, nnThe first n operand in this assemb

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual261Condition Bits AffectedNone.ExampleIf the Carry flag (i.e., the C flag in F Register)

Z80 Instruction Set UM008007-0715262Z80 CPUUser ManualJR eOperationPC ← PC + eOp CodeJROperandeDescriptionThis instruction provides for unconditiona

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual263Location Instruction480 18481 03482 –483 –484 –485 ← PC after jump

Z80 Instruction Set UM008007-0715264Z80 CPUUser ManualJR C, eOperationIf C = 0, continueIf C = 1, PC ← PC+ eOp CodeJROperandsC, eDescriptionThis in

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual265ExampleThe Carry flag is set and it is required to jump back four locations from 480.

Z80 Instruction Set UM008007-0715266Z80 CPUUser ManualJR NC, eOperationIf C = 1, continueIf C = 0, PC ← PC + eOp CodeJROperandsNC, eDescriptionThis

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual267ExampleThe Carry Flag is reset and it is required to repeat the jump instruction. The

Architectural Overview UM008007-071516Z80 CPUUser ManualPower-Down Release CycleThe system clock must be supplied to the Z80 CPU to release the powe

Z80 Instruction Set UM008007-0715268Z80 CPUUser ManualJR Z, eOperationIf Z = 0, continueIf Z = 1, PC ← PC + eOp CodeJROperandsZ, eDescriptionThis i

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual269ExampleThe Zero Flag is set and it is required to jump forward five locations from add

Z80 Instruction Set UM008007-0715270Z80 CPUUser ManualJR NZ, eOperationIf Z = 1, continueIf Z = 0, PC ← pc + eOp CodeJROperandsNZ, eDescriptionThis

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual271ExampleThe Zero Flag is reset and it is required to jump back four locations from 480.

Z80 Instruction Set UM008007-0715272Z80 CPUUser ManualJP (HL)OperationPC ← HL Op CodeJPOperand(HL)DescriptionThe Program Counter (PC) is loaded with

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual273JP (IX)Operationpc ← IXOp CodeJPOperand(IX)DescriptionThe Program Counter (PC) is load

Z80 Instruction Set UM008007-0715274Z80 CPUUser ManualJP (IY)OperationPC ← IYOp CodeJPOperand(IY)DescriptionThe Program Counter (PC) is loaded with

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual275DJNZ, eOperationB ← B – 1If B = 0, continueIf B ≠ 0, PC ← PC + eOp CodeDJNZOperandeDes

Z80 Instruction Set UM008007-0715276Z80 CPUUser ManualCondition Bits AffectedNone.ExampleA typical software routine is used to demonstrate the use o

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual277Call and Return GroupThe following call and return group instructions are each describ

UM008007-0715 Interrupt ResponseZ80 CPUUser Manual17Interrupt ResponseAn interrupt allows peripheral devices to suspend CPU operation and force the

Z80 Instruction Set UM008007-0715278Z80 CPUUser ManualCALL nnOperation(SP – 1) ← PCH, (SP – 2) ← PCL, PC ← nnOp CodeCALLOperandnnThe first of the tw

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual279ExampleThe Program Counter contains 1A47h, the Stack Pointer contains 3002h, and memor

Z80 Instruction Set UM008007-0715280Z80 CPUUser ManualCALL cc, nnOperationIF cc true: (sp – 1) ← PCH(sp – 2) ← PCL, pc ← nnOp CodeCALLOperandscc, nn

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual281If cc is true:If cc is false:Condition Bits AffectedNone.ExampleThe C Flag in the F Re

Z80 Instruction Set UM008007-0715282Z80 CPUUser ManualRETOperationpCL ← (sp), pCH ← (sp+1)Op CodeRETOperandsNone.DescriptionThe byte at the memory l

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual283RET ccOperationIf cc true: PCL ← (sp), pCH ← (sp+1)Op CodeRETOperandccDescriptionIf co

Z80 Instruction Set UM008007-0715284Z80 CPUUser ManualIf cc is true, then the following data is returned:If cc is false, then the following data is

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual285RETIOperationReturn from InterruptOp CodeRETIOperandsNone.DescriptionThis instruction

Z80 Instruction Set UM008007-0715286Z80 CPUUser ManualB generates an interrupt and is acknowledged. The interrupt enable out, IEO, of B goes Low, bl

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual287RETNOperationReturn from nonmaskable interruptOp CodeRETNOperandsNone.DescriptionThis

UM008007-0715 Revision HistoryZ80 CPUUser ManualiiiRevision HistoryEach instance in the following revision history table reflects a change to this d

Architectural Overview UM008007-071518Z80 CPUUser ManualThe state of IFF1 is used to inhibit interrupts while IFF2 is used as a temporary storage lo

Z80 Instruction Set UM008007-0715288Z80 CPUUser ManualThat address begins an interrupt service routine that ends with a RETN instruction. Upon the e

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual289RST pOperation(SP – 1) ← PCH, (SP – 2) ← PCL, PCH ← 0, PCL ← POp CodeRSTOperandpDescri

Z80 Instruction Set UM008007-0715290Z80 CPUUser ManualExampleIf the Program Counter contains 15B3h, then upon the execution of an RST 18h (object co

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual291Input and Output GroupThe following input and output group instructions are each descr

Z80 Instruction Set UM008007-0715292Z80 CPUUser ManualIN A, (n)OperationA ← (n)Op CodeINOperandsA, (n)DescriptionThe operand n is placed on the bott

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual293IN r (C)Operationr ← (C)Op CodeINOperandsr, (C)DescriptionThe contents of Register C a

Z80 Instruction Set UM008007-0715294Z80 CPUUser ManualCondition Bits AffectedS is set if input data is negative; otherwise, it is reset.Z is set if

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual295INIOperation(HL) ← (C), B ← B – 1, HL ← HL + 1Op CodeINIOperandsNone.DescriptionThe co

Z80 Instruction Set UM008007-0715296Z80 CPUUser ManualExampleRegister C contains 07h, Register B contains 10h, the HL register pair contains 1000h,

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual297INIROperation(HL) ← (C), B ← B – 1, HL ← HL +1Op CodeINIROperandsNone.DescriptionThe c

UM008007-0715 CPU ResponseZ80 CPUUser Manual19CPU ResponseThe CPU always accepts a nonmaskable interrupt. When this nonmaskable interrupt is accepte

Z80 Instruction Set UM008007-0715298Z80 CPUUser ManualCondition Bits AffectedS is unknown.Z is set.H is unknown.P/V is unknown.N is set.C is not aff

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual299INDOperation(HL) ← (C), B ← B – 1, HL ← HL – 1Op CodeINDOperandsNone.DescriptionThe co

Z80 Instruction Set UM008007-0715300Z80 CPUUser ManualExampleRegister C contains 07h, Register B contains 10h, the HL register pair contains 1000h,

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual301INDROperation(HL) ← (C), B ← 131, HL ← HL1Op CodeINDROperandsNone.DescriptionThe conte

Z80 Instruction Set UM008007-0715302Z80 CPUUser ManualCondition Bits AffectedS is unknown.Z is set.H is unknown.P/V is unknown.N is set.C is not aff

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual303OUT (n), AOperation(n) ← AOp CodeOUTOperands(n), ADescriptionThe operand n is placed o

Z80 Instruction Set UM008007-0715304Z80 CPUUser ManualOUT (C), rOperation(C) ← rOp CodeOUTOperands(C), rDescriptionThe contents of Register C are pl

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual305Condition Bits AffectedNone.ExampleIf Register C contains 01h and the D Register conta

Z80 Instruction Set UM008007-0715306Z80 CPUUser ManualOUTIOperation(C) ← (HL), B ← B – 1, HL ← HL + 1Op CodeOUTIOperandsNone.DescriptionThe contents

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual307ExampleIf Register C contains 07h, Register B contains 10h, the HL register pair conta

Architectural Overview UM008007-071520Z80 CPUUser ManualIn Mode 2, the programmer maintains a table of 16-bit starting addresses for every inter-rup

Z80 Instruction Set UM008007-0715308Z80 CPUUser ManualOTIROperation(C) ← (HL), B ← B – 1, HL ← HL + 1Op CodeOTIROperandsNone.DescriptionThe contents

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual309If B = 0:Condition Bits AffectedS is unknown.Z is set.H is unknown.P/V is unknown.N is

Z80 Instruction Set UM008007-0715310Z80 CPUUser ManualOUTDOperation(C) ← (HL), B ← B – 1, HL ← HL – 1Op CodeOUTDOperandsNone.DescriptionThe contents

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual311ExampleIf Register C contains 07h, Register B contains 10h, the HL register pair conta

Z80 Instruction Set UM008007-0715312Z80 CPUUser ManualOTDROperation(C) ← (HL), B ← B – 1, HL ← HL – 1Op CodeOTDROperandsNone.DescriptionThe contents

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual313If B = 0:Condition Bits AffectedS is unknown.Z is set.H is unknown.P/V is unknown.N is

Customer Support UM008007-0715314Z80 CPUUser ManualCustomer SupportTo share comments, get your technical questions answered, or report issues you ma

UM008007-0715 Hardware and Software ImplementationZ80 CPUUser Manual21Hardware and Software ImplementationThis chapter is an introduction to impleme

Hardware and Software Implementation UM008007-071522Z80 CPUUser ManualBecause the Z80 CPU requires only a single 5 V power supply, most small system

UM008007-0715 Memory Speed ControlZ80 CPUUser Manual23In Figure 20, the address space is portrayed in hexadecimal notation. Address bit A10 sep-arat

Hardware and Software Implementation UM008007-071524Z80 CPUUser ManualFigure 21. Adding One Wait State to an M1 CycleFigure 22. Adding One Wait Stat

UM008007-0715 Interfacing Dynamic MemoriesZ80 CPUUser Manual25Interfacing Dynamic MemoriesEach individual dynamic RAM space includes its own specifi

Hardware and Software Implementation UM008007-071526Z80 CPUUser ManualSoftware Implementation ExamplesThe Z80 instruction set provides the user with

UM008007-0715 Specific Z80 Instruction ExamplesZ80 CPUUser Manual27Specific Z80 Instruction ExamplesExample 1When a 737-byte data string in memory l

UM008007-0715 Table of ContentsZ80 CPUUser ManualivTable of ContentsRevision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Hardware and Software Implementation UM008007-071528Z80 CPUUser ManualLD HL, DATA ;ADDRESS OF FIRST BYTELD B, COUNT ;SHIFT COUNTXOR A ;CLEAR ACCUMUL

UM008007-0715 Programming Task ExamplesZ80 CPUUser Manual29SBC A, (HL) ;SUBTRACT (HL) FROM ACCDAA ;ADJUST RESULT TO DECIMAL CODED VALUELD (HL), A ;S

Hardware and Software Implementation UM008007-071530Z80 CPUUser Manual19 ; l unused20 ; ix pointer into data array21 ; iy unused22 ;0000 222600 23 s

UM008007-0715 Programming Task ExamplesZ80 CPUUser Manual31The program outlined in Table 3 multiplies two unsigned 16-bit integers, leaving the resu

Z80 CPU Instructions UM008007-071532Z80 CPUUser ManualZ80 CPU InstructionsThe Z80 CPU can execute 158 different instruction types including all 78 o

UM008007-0715 Instruction TypesZ80 CPUUser Manual33An example of an arithmetic operation is adding the Accumulator to the contents of an external me

Z80 CPU Instructions UM008007-071534Z80 CPUUser ManualAddressing ModesMost of the Z80 instructions operate on data stored in internal CPU registers,

UM008007-0715 Modified Page Zero AddressingZ80 CPUUser Manual35Modified Page Zero AddressingThe Z80 contains a special single-byte CALL instruction

Z80 CPU Instructions UM008007-071536Z80 CPUUser ManualExtended AddressingExtended Addressing provides for two bytes (16 bits) of address to be inclu

UM008007-0715 Register AddressingZ80 CPUUser Manual37complement number. Indexed addressing greatly simplifies programs using tables of data because

Table of Contents UM008007-0715vZ80 CPUUser ManualAddressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z80 CPU Instructions UM008007-071538Z80 CPUUser Manualparentheses around the name of the register that is to be used as the pointer. For example, th

UM008007-0715 Load and ExchangeZ80 CPUUser Manual39The Z80 instruction mnemonics consist of an op code and zero, one, or two operands. Instructions

Z80 CPU Instructions UM008007-071540Z80 CPUUser ManualTable 5. 8-Bit Load Group LD SourceImplied Register Reg Indirect Indexed Ext. Imm.Destination

UM008007-0715 Load and ExchangeZ80 CPUUser Manual41Descriptions of the 8-Bit Load Group instructions begin on page 68.The parentheses around the HL

Z80 CPU Instructions UM008007-071542Z80 CPUUser ManualIn this figure, note that the low-order portion of the address is always the first operand.The

UM008007-0715 Load and ExchangeZ80 CPUUser Manual43In this figure, note that with any indexed addressing, the displacement always follows directly a

Z80 CPU Instructions UM008007-071544Z80 CPUUser ManualDescriptions of the 16-Bit Load Group instructions begin on page 96.These 16-bit load operatio

UM008007-0715 Block Transfer and SearchZ80 CPUUser Manual45In all extended immediate or extended addressing modes, the low-order byte always appears

Z80 CPU Instructions UM008007-071546Z80 CPUUser ManualAfter the programmer initializes these three registers, any of these four instructions can be

UM008007-0715 Arithmetic and LogicalZ80 CPUUser Manual47Descriptions of the Exchange, Block Transfer, and Search Group instructions begin on page 12

UM008007-0715 Table of ContentsZ80 CPUUser ManualviLD (HL), n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z80 CPU Instructions UM008007-071548Z80 CPUUser ManualDescriptions of the 8-Bit Arithmetic Group instructions begin on page 142.The result of the op

UM008007-0715 Arithmetic and LogicalZ80 CPUUser Manual49The INC and DEC instructions specify a register or a memory location as both the source and

Z80 CPU Instructions UM008007-071550Z80 CPUUser ManualDescriptions of the General-Purpose Arithmetic and CPU Control Groups instructions begin on pa

UM008007-0715 Rotate and ShiftZ80 CPUUser Manual51Rotate and ShiftA major feature of the Z80 CPU is to rotate or shift data in the Accumulator, any

Z80 CPU Instructions UM008007-071552Z80 CPUUser ManualDescriptions of the Rotate and Shift Group instructions begin on page 202.Figure 39. Rotates a

UM008007-0715 Bit ManipulationZ80 CPUUser Manual53Bit ManipulationThe ability to set, reset, and test individual bits in a register or memory locati

Z80 CPU Instructions UM008007-071554Z80 CPUUser ManualTest Bit (cont’d.)6DD FDC8 C8 C8 C8 C8 C8 C8 C8 C8 C877 70 71 72 73 74 75 76 d d76 767DD DDC8

UM008007-0715 Bit ManipulationZ80 CPUUser Manual55Rest BitRES(cont’d.) 7DD DDC8 C8 C8 C8 C8 C8 C8 C8 C8 C8BF B8 89 8A B8 8C BD 9E d dBE BESet Bit

Z80 CPU Instructions UM008007-071556Z80 CPUUser ManualRegister addressing can specify the Accumulator or any general-purpose register on which an op

UM008007-0715 Jump, Call, and ReturnZ80 CPUUser Manual57Descriptions of the Jump Group instructions begin on page 258.Three types of Register Indire

Table of Contents UM008007-0715viiZ80 CPUUser ManualLDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z80 CPU Instructions UM008007-071558Z80 CPUUser Manualgram Counter to form a jump address. The call and return instructions allow for simple subrout

UM008007-0715 Input/OutputZ80 CPUUser Manual59Descriptions of the Call and Return Group instructions begin on page 277.Input/OutputThe Z80 CPU conta

Z80 CPU Instructions UM008007-071560Z80 CPUUser ManualTable 17. Input GroupImmediate(n)RegisterIndirect)(c)InputDestinationInput INRegisterAddressA

UM008007-0715 CPU Control GroupZ80 CPUUser Manual61Descriptions of the Input and Output Group instructions begin on page 291.CPU Control GroupTable

Z80 CPU Instructions UM008007-071562Z80 CPUUser ManualIf Mode 0 is set, the interrupting device can insert any instruction on the data bus and allow

UM008007-0715 Z80 Instruction SetZ80 CPUUser Manual63Z80 Instruction SetThis chapter provides a description of the assembly language instructions av

Z80 Instruction Set UM008007-071564Z80 CPUUser ManualEach of these two Flag registers contains 6 bits of status information that are set or cleared

UM008007-0715 Decimal Adjust Accumulator FlagZ80 CPUUser Manual65Decimal Adjust Accumulator FlagThe Decimal Adjust Accumulator (DAA) instruction use

Z80 Instruction Set UM008007-071566Z80 CPUUser ManualDuring the CPI, CPIR, CPD, and CPDR search instructions and the LDI, LDIR, LDD, and LDDR block

UM008007-0715 Sign FlagZ80 CPUUser Manual67Sign FlagThe Sign Flag (S) stores the state of the most-significant bit of the Accumulator (bit 7). When

UM008007-0715 Table of ContentsZ80 CPUUser ManualviiiINC IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z80 Instruction Set UM008007-071568Z80 CPUUser Manual8-Bit Load GroupThe following 8-bit load instructions are each described in this section. Simpl

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual69LD r, r'Operationr, ← r′Op CodeLDOperandsr, r′DescriptionThe contents of any regis

Z80 Instruction Set UM008007-071570Z80 CPUUser ManualLD r,nOperationr ← nOp CodeLDOperandsr, nDescriptionThe 8-bit integer n is loaded to any regist

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual71ExampleUpon the execution of an LD E, A5h instruction, Register E contains A5h.

Z80 Instruction Set UM008007-071572Z80 CPUUser ManualLD r, (HL)Operationr ← (HL)Op CodeLDOperandsr, (HL)DescriptionThe 8-bit contents of memory loca

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual73LD r, (IX+d)Operationr ← (IX+d)Op CodeLDOperandsr, (IX+d)DescriptionThe (IX+d) operand

Z80 Instruction Set UM008007-071574Z80 CPUUser ManualExampleIf Index Register IX contains the number 25AFh, the instruction LD B, (IX+19h) allows th

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual75LD r, (IY+d)Operationr ← (IY+D)Op CodeLDOperandsr, (lY+d)DescriptionThe operand (lY+d)

Z80 Instruction Set UM008007-071576Z80 CPUUser ManualExampleIf Index Register IY contains the number 25AFh, the instruction LD B, (IY+19h) allows th

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual77LD (HL), rOperation(HL) ← rOp CodeLDOperands(HL), rDescriptionThe contents of register

Table of Contents UM008007-0715ixZ80 CPUUser ManualCALL nn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z80 Instruction Set UM008007-071578Z80 CPUUser ManualExampleIf the contents of register pair HL specify memory location 2146h and Register B contain

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual79LD (IX+d), rOperation(IX+d) ← rOp CodeLDOperands(IX+d), r DescriptionThe contents of re

Z80 Instruction Set UM008007-071580Z80 CPUUser ManualExampleIf the C register contains byte 1Ch, and Index Register IX contains 3100h, then the inst

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual81LD (IY+d), rOperation(lY+d) ← rOp CodeLDOperands(lY+d), rDescriptionThe contents of res

Z80 Instruction Set UM008007-071582Z80 CPUUser ManualExampleIf the C register contains byte 48h, and Index Register IY contains 2A11h, then the inst

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual83LD (HL), nOperation(HL) ← nOp CodeLDOperands(HL), nDescriptionThe n integer is loaded t

Z80 Instruction Set UM008007-071584Z80 CPUUser ManualLD (IX+d), nOperation(IX+d) ← nOp CodeLDOperands(IX+d), nDescriptionThe n operand is loaded to

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual85LD (IY+d), nOperation(lY+d) ← nOp CodeLDOperands(lY+d), nDescriptionThe n integer is lo

Z80 Instruction Set UM008007-071586Z80 CPUUser ManualLD A, (BC)OperationA ← (BC)Op CodeLDOperandsA, (BC)DescriptionThe contents of the memory locati

UM008007-0715 Z80 Instruction DescriptionZ80 CPUUser Manual87LD A, (DE)OperationA ← (DE)Op CodeLDOperandsA, (DE)DescriptionThe contents of the memor